[전자공학종합설계] 2. RISC-V pipelined CPU implemented in verilog HDL

전자공학종합설계의 3번째 포스팅입니다.

 

아직 미완이라 일단 소스코드만 올려놓음.. 내일 글로 정리하겠습니다.

`define INST_SIZE   32
`define ADDR_SIZE   64

module CPU (
    input clk ,rst
);
   // IF stage
    wire    [`INST_SIZE-1:0]    Instruction; // output of IF/ID
    wire    [`ADDR_SIZE-1:0]    IF_stage_PC;
    
    wire    [`ADDR_SIZE-1:0]    IF_stage_PC_p_4;
    wire    [`ADDR_SIZE-1:0]    IF_stage_PC_p_offset;
    

    // ID stage
    wire    [2:0]               ID_stage_EX_control_sig;
    wire    [2:0]               ID_stage_MEM_control_sig;
    wire    [1:0]               ID_stage_WB_control_sig;
    wire    [6:0]               op_code;
    // Branch, MemRead, MemtoReg, ALUop, MemWrite, ALUSrc, RegWrite , 7bit of Control signal

    wire    [`ADDR_SIZE-1:0]    ID_stage_PC;
    
    wire    [`INST_SIZE-1:0]    Inst_for_address;
    wire    [4:0]               ID_stage_reg_destination;

    wire    [4:0]               rs1, rs2, rd;
    wire    [3:0]               ID_stage_funct_field;
    
    wire    [`ADDR_SIZE-1:0]    ID_Read_data_1;
    wire    [`ADDR_SIZE-1:0]    ID_Read_data_2;
    wire    [`ADDR_SIZE-1:0]    ImmGen_result;

    // EX stage

    wire    [`ADDR_SIZE-1:0]    EX_stage_PC;
    wire    [2:0]               EX_stage_MEM_control_sig;
    wire    [1:0]               EX_stage_WB_control_sig;

    wire    [1:0]               ALU_op;
    wire                        ALU_src;

    wire    [4:0]               EX_stage_reg_destination;

    wire    [`ADDR_SIZE-1:0]    EX_stage_Read_data_1;
    wire    [`ADDR_SIZE-1:0]    EX_stage_Read_data_2;
    wire    [`ADDR_SIZE-1:0]    EX_stage_Immediate;
    wire    [3:0]               EX_stage_funct_field;

    // MEM stage
    wire    [1:0]               MEM_stage_WB_cotrol_sig;
    wire                        PC_Scr;



    // IF stage
    assign      IF_stage_PC_4           =       IF_stage_PC + 4;

    MUX_2_to_1 mux0         (   .in_0                       (IF_stage_PC_p_4),
                                .in_1                       (IF_stage_PC_p_bo),
                                .sel                        (PCSrc),
                                .out_0                      (IF_stage_PC));
    ///////////////////////////////////////////////////////////////////////////////////
    IF_ID_register IFIDr(       .clk                        (clk),
                                .rst                        (rst),
                                .IF_PC                      (IF_stage_PC),
                                .instruction_out            (Instruction),
                                
                                .IF_PC_out                  (ID_stage_PC),
                                .instruction_out            (Instruction));
    ///////////////////////////////////////////////////////////////////////////////////
    // ID stage

    assign      rs1                     =       Instruction[19:15];
    assign      rs2                     =       Instruction[24:20];
    assign      ID_stage_funct_field    =       {Instruction[30], Instruction[14:12]};
    
    assign      opcode                  =       Instruction[6:0];
    assign      Inst_for_address        =       Instruction;
    assign      reg_destination         =       Instruction[11:7];


    Registers regi();
    ImmediateGenerator immgen(  .instruction                (Instruction),
                                .immediate                  (ImmGen_result));

    Control_signal_unit csu(    .opcode                     (op_code),
                                .EX_control                 (ID_stage_EX_control_sig),
                                .MEM_control                (ID_stage_MEM_control_sig),
                                .WB_control                 (ID_stage_WB_control_sig));
    ///////////////////////////////////////////////////////////////////////////////////
    ID_EX_register IDEXr(       .clk                        (clk),
                                .rst                        (rst),

                                .EX_control_sig             (ID_stage_EX_control_sig),
                                .MEM_control_sig            (ID_stage_MEM_control_sig),
                                .WB_control_sig             (ID_stage_WB_control_sig),

                                .ID_PC                      (ID_stage_PC),
                                .ID_Read_data_1             (ID_Read_data_1),
                                .ID_Read_data_2             (ID_Read_data_2),
                                .Immediate                  (ImmGen_result),                  
                                .Funct_field                (ID_stage_funct_field),
                                .ID_register_destination    (reg_destination),
                                
                                .MEM_control_sig_out        (EX_stage_MEM_control_sig),
                                .WB_control_sig_out         (EX_stage_WB_control_sig),
                                .ALU_op                     (ALU_op),
                                .ALU_src                    (ALU_src),
                                
                                .ID_PC_out                  (EX_stage_PC),
                                .ID_Read_data_1_out         (EX_stage_Read_data_1),
                                .ID_Read_data_2_out         (EX_stage_Read_data_2),
                                .Immediate_out              (EX_stage_Immediate),
                                .Funct_field_out            (EX_stage_funct_field),

                                .ID_register_destination_out  (EX_stage_reg_destination));
    ///////////////////////////////////////////////////////////////////////////////////
    // EX stage
    

    EX_MEM_register EXMEMr();

    MEM_WB_register MEMWBr();

endmodule